Cost Analysis and Cost-Driven IP Reuse Methodology via 2.5D/3D Heterogeneous Integration
Abstract
Cost Analysis and Cost-Driven IP Reuse Methodology via 2.5D/35 Heterogeneous Integration Yuan Xie Professor, ECE department University of California, Santa Barbara yuanxie@ece.ucsb.edu This project aims at enabling future common heterogeneous integration and IP-reuse strategies, with a focus on cost analysis and cost-driven IP reuse methodology via 2.5D/3D heterogeneous integration. Intellectual property (IP) reuse is essential to meet the challenges of IC design productivity improvement, design quality, and shorten the time-to-market. IP reuse has been explored for many years since the emerging of SOC design methodologies. It has been an efficient way to reduce the design cost for high-volume digital SOC designs. 2.5D integration is to integrate multiple IC dies on a same package with interposer technology, while 3D integration is to integrate multiple IC dies on a same package with more advanced stacked chip technologies, such as through-silicon-via (TSV) technology or monolithic 3D technology where multiple active device layers are grown on the same silicon substrates.The major goal of combining IP reuse and heterogeneous integration is to lower the design and fabrication cost, and accelerate the technology adoption. The advantages of any performance/power benefits of an emerging technology ultimately have to be translated into cost savings when a design strategy has to be decided. Consequently, it is very important to perform cost analysis at the early design stage to explore various design options, such as 2D SOC integration or 2.5D/3D heterogeneous integrations. The proposed project will build upon the PIÕs prior expertise and experience on 2.5D/3D architecture and design methodologies, and explore possible directions to enable an effective IP reuse strategy for heterogeneous integration. The proposed project consists of two tasks that address the challenges. The first task focuses on cost analysis and cost-driven IP reuse methodology exploration. The work will develop a set of cost analysis tools that can be integrate into traditional design automation flow, in order to facilitate design space explorations and help architects understand which approaches should be adopted. A cost-driven design methodology, which is the close coupling between cost analysis and 2.5D/3D architecture-physical design co optimization, will also be developed. The second task will develop two interconnect architectures that can help enable IP-reuse strategy. The first one is an interposer-based Interconnect Service Layer (ISL) architecture. The second one is a TSV-based ISL architecture. The design will be simulated with architecture simulation platform to demonstrate the feasibility of the proposed work.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jun 10, 2016
- Source ID
- N000141612087
Entities
People
- Yuan Xie
Organizations
- Office of Naval Research
- United States Navy
- University of California, Santa Barbara