THIS IS A CONTINUATION OF N00014-14-1-0717 A Unified Theory and Practice: Secure, Dependable, and Resilient Information Infastructure
Abstract
Our goal is to develop the scientific knowledge and technological foundation that will enable the rapid development of advanced software for information dominance. This foundation shall enable the development of ? A middleware to provide applications with consistent views and commands across wired and wireless networks in real time whenever physically possible. Achieving consistency in real time has been a great common challenge for distributed real time computing applications. ? Multicore computing nodes that are not only secured and resilient against attacks but also have high real time performance. Such secured, resilient and high performance computing platforms are vital to the implementation of information dominance applications and to the middleware that links distributed applications. This is a tall order. Fortunately, we have already made great advancement, and we will build on our successes. Our achievements include: ? Physically Asynchronous Logically Synchronous (PALS) architecture as the foundation for middleware. With PALS middleware, the model checking time of a dual redundant flight control prototype at Rockwell Collins dropped from 35 hours to less than 30 seconds. Lockheed Martin study showed that PALS middleware provided real time performance that is 2 orders higher than Navy requirements for submarine control. ? Single Core Equivalent (SCE) technology that prevents pathological interactions in the sharing of common resources, e.g., last level cache, between cores. Lockheed Martin benchmark shows that SCE technology improves hard real time performance up to 600%. ? SecureCore technology that enables the creation of secured cores within a multicore chip. Inside a secured core, protected software will have: o One-way visibility: Ability to closely monitor the states of the application cores. However, the monitoring activity is invisible from the application cores. o One-way controllability: The secured core can wipe the software in application cores clean and reload new ones from secured storage, but not vice versa. The integration of SecureCore architecture with Simplex architecture and with SCE technology creates multicore processors with much higher real time performance and greatly improved security and resilience against attacks. Together with PALS middleware, we are closing in towards our goal. However, there are still significant scientific and technological challenges. ? Science: PALS in its current form supports only wired networks, but vehicles are mobile and connected by wireless networks. To provide consistent distributed views and commands whenever physically possible requires the scientific understanding of statistically consistent distributed real time computing. ? Technology: A multicore chipÕs core is faster than the vast majority of legacy single-core chips. Thus, SCE technology paves the way for the rapid migration and development of real-time software for multicore. Multicore chips also open the door for high real time performance applications, where a simple application requires the use of multiple cores. This calls for Physically Multicore Logically Single-core technology with the performance of multicore but the simplicity of developing single core real time software. ? Transition to Practice: To facilitate technology transition, we will working with industry from the start. We will begin with model applications from industry and use them to guide investigation and to validate the usability of candidate solutions. Next, we will assist industry to develop application prototypes in their own labs.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jun 10, 2016
- Source ID
- N000141612151
Entities
People
- Lui R. Sha
Organizations
- Office of Naval Research
- United States Navy
- University of Illinois Urbana–Champaign