Basic Research Issues Limiting Performance of Josephson Junction Integrated Circuits
Abstract
Basic Research Issues Limiting Performance of Josephson Junction Integrated CircuitsStatement of WorkFunds are provided to pursue 11 narrowly focused subefforts focused on the themes of A) Materials effects, (B) Current Flow through Circuit Passives, C) Signal/Data Input/Output interfaces across the 300-4K signal amplitude divide, D) Superconducting Digital Signal Processing, and E) ADC architectures enabled by circuit parallelization. The efforts are unified by the desire to improve the ability of simulation tools to accurately predict the behavior of the physically realized structures as they become more complex and spatially dense. Significant improvements in analog to digital converter (ADC) performance is expected to be enabled by this still basic research.ObjectiveThe objective of this grant is to improve the fidelity of the theoretical models used to describe the flow of superconducting currents through simple circuits (such as balanced comparators and SFQ transmitters/receivers) in order to allow reliable prediction of fabricated circuit performance via simulation. This advance on the current state of the art is essential if the full performance benefit of superconducting electronics is ever to be realized and for the realization of circuit complexity competitive with silicon in the 1990s.ApproachEleven different areas of concern have been identified that fall into 5 different themes: A) Materials, (B) Current Flow through Circuit Passives, C) Signal/Data Input/Output interfaces across the 300-4K signal amplitude divide, D) Superconducting Digital Signal Processing, and E) ADC architectures enabled by circuit parallelization. The materials theme focuses on the electrical engineering model of a Josephson junction s dynamical (SNS) switching behavior and in particular its method of including the detailed realities revealed by the static current voltage curve which are dependent on the specific materials out of which the electrodes and tunnel barrier are composed and the thicknesses of these layers. Both the loss of hysteresis in the IV for high transparency barriers and the distinctions between s wave (Nb) and d wave (YBCO) pairing will be included. This sub-effort also requires completion of the inclusion of Monte Carlo simulation of the effects of statistical device variation on circuit margins and the development of back annotation in timing analysis. Testing will include multi-chip modules composed of die with different critical current Nb devices and a mixture of Nb devices with structures made of MgB2 and or YBCO. The second theme focuses on understanding and correcting the simulation errors recently discovered in the modeling of current vias and inductances within the currently used >20 patterned layer device structures. The originally sufficient choice of treating each strip of superconductor as a homogeneous, single order parameter phase object carrying a uniform pair current (Jc) and largely ignoring inter-element parasitics is no longer adequate. Vias in power distribution lines will be the first structures to be worked as some designed that way are going normal in actual circuits. It may be necessary to grid the structures on length scales smaller than the ~40 nm superconducting coherence length and advance the state of the art of modeling of phase slip centers in nTrons to achieve adequate predictive abilities for designs to be successful. The work will however start with the non-uniform current densities that appear due to self-B-field effects and their interactions with via structure edges. Vertical current flow in pads, especially in hybrid technology MCM will also be checked. The impact of vertical currents in vias and moat edges on in plane local magnetic fields at nearby switching devices (JJ) will also be explored to check if it is a source of effective Jc variation. Once that work is complete, the focus can shift to the production and distribution of low jitter on-chip clock signals using
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 08, 2016
- Source ID
- N000141612291
Entities
People
- Deepnarayan Gupta
Organizations
- Hypres
- Office of Naval Research
- United States Navy