Mobile Robot Onboard Accelerated Computation
Abstract
Real~time robot visual and navigation learning requires extensive computational resources. Racks of general~purpose computer processors fill this role but relegate their robots to controlled environments due to the weight, size, and power consumption of server farms. FPGAs contain the ability to dynamically assemble into accelerators that can be optimized for specific algorithms. The massive parallelism and low power of FPGA circuitry provides the opportunity to mobilize highlyparallel algorithms, i.e. those with high Amdahl fractions, which is a generally uncommon trait for software but known to be inherent in brain~circuit algorithms. It is being proposed by the team to mobilize a set of well~studied brain~circuit algorithms by adapting them for execution on a novel low~power Processor~FPGA design; the resulting device will be tested on mobile robots for its ability toaccelerate learning and increase battery life in on~board robot use.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 12, 2016
- Source ID
- N000141612359
Entities
People
- Richard Granger
Organizations
- Board of Trustees of Dartmouth College
- Office of Naval Research
- United States Navy