A Universal and Reusable Scheme for Analog, Mixed Signal and Digital Heterogeneous Integration
Abstract
A Universal and Reusable Scheme for Analog, Mixed Signal and Digital Heterogeneous Integration. Over the last 50 years, conventional scaling (Moore’s law) has provided continuous improvement in semiconductor device/circuit technology and has resulted in unprecedented advancement in electronic systems. Highly functional systems-on-chip have resulted - combining RF/analog with signal conversion with sophisticated signal processing and complex digital computation. SoCs have brought tremendous performance and cost-effectiveness to defense applications. Historically, CMOS transistor technology scaling has driven the power cost and performance of SoCs. However, traditional scaling is saturating in all three measures due to challenges in both development and manufacturing. In addition, conventional scaled silicon CMOS is not optimized for high performance analog/RF. To achieve breakthrough system performance, transistor technology based on advanced III-V materials systems such as GaN are needed. Therefore, heterogeneous integration of these advanced III-V technology with silicon VLSI is very attractive for many DoD as well as high-end commercial applications. While ONR programs such as DAHI seek to realize chiplet and/or transistor level heterogeneous integration, other approaches such as 3D or interposer integration have advantages in combining existing silicon VLSI and a diverse portfolio of advanced GaN, InGaAs, and GaAs technologies. In this proposal, we seek to address the technology challenge of connecting, with IP reuse, an analog die with minimal digital content to a general purpose processor with high bandwidth, low latency and excellent signal integrity through heterogeneous integration on an a silicon-based Interconnection Fabric (IF) that adopts the tight interconnect schemes of silicon with the heterogeneous nature of Printed Circuit boards. We envision using a silicon substrate as the system substrate with a “translator chip” that can facilitate the analog signal and digital control signals transfer between the advanced III-V MMIC and the silicon SoC die, all attached to this silicon substrate. Key technology innovations on this silicon substrate include a versatile interconnect fabric with fine pitch interconnects comparable to the fat wire levels on a silicon processor connected with as fine a pitch as possible. Note that fine pitch is needed to connect the “translator” chip to the analog and digital chips to increase the overall number of channels. Another key innovation is the translator chip itself and the silicon substrate can be fabricated using commodity silicon technology and processes. In this project, we will explore assembly technique that allows us to connect these dies to interconnect fabric by micro thermal compression bonding (?-TCB) at fine pitch with minimal to no solder. It is envisioned that the translator chip is re-usable either as a cost effective hard chiplet or integrated into the Silicon interconnect fabric as hard IP or a “synthesizable hardened“ macro that can be integrated into a processor CMOS. The hard chiplet made be made as an off-the-shelf item that is easily available and royalty free for DoD approved parties. We will also work closely with Prof. Koyanagi’s team at GINTI/Tohoku University to apply and extend techniques he has developed to this problem.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Nov 23, 2016
- Source ID
- N000141612639
Entities
People
- Subramanian Iyer
Organizations
- Office of Naval Research
- United States Navy
- University of California, Los Angeles