HIGH-SPEED, SCALABLE, SYSTEM LEVEL, REAL-TIME SIMULATION
Abstract
The scope of the research program effort is: to merge the use of latency based approaches (LIMand LB-LMC) for high-speed real time simulation of power electronics system, to investigate theuse of a multi-FPGA solution for very large systems simulation, and to investigate and developcode-generation capabilities. The research effort will be organized in 4 tasks over 3 years.Task1: Formulation and implementation of simulation methods based on LB-LMC and LIM.In this task we will formulate, develop and test the implementation of the solver based on LIMand LB-LMC on a single FPGA (Virtex-7) platform. We will perform an analytical analysis ofthe method stability and accuracy characteristics, and will measure the performance of its FPGAimplementation. The two main metrics that will be used will be: execution speed (smaller timestep usable) and scalability (both in terms of execution speed and of resources use). In additionto these two quantitative metrics a more qualitative analysis of modeling limit andimplementation aspects (mainly in relation to code generation) will be performed.Task 2: Drivers development for multi-PFGA hardware set-upTo support the work of Task 3 (Multi-FPGA solver implementation and testing) we will need toset-up a dedicated hardware. While we will be using COTS hardware we will still need todevelop drivers for FPGA to FPGA communication and for memory access behind what wealready developed for the actual single-FPGA set-up.Figure 9 Solution Flow Implementation13Task 3: Multi-FPGA solver implementation and testingIn this task we will precede modifying - for multi-FPGA execution - the simulation approachdefined in task one. The foci of this task will be to analyze how the communication betweenFPGAs affects the simulation performance and to investigate solutions to limit the adverseeffects of the communication on simulation time step. In particular we will investigate methodsto compensate for those delays directly in simulation models.Task 4: Co-generation capabilities and library implementationWe will develop code generation capabilities so that simulation VHDL code can be directlygenerated from a generic net-list representation of the components connections. A net-listapproach will be used to provide a generalized solution, i.e. not related to any specific simulationtools, so that in the future the net-list with appropriate interfaces could be extracted from acommercial simulation tool or from a database like LEAPS. As part of this task we will alsodevelop a small library of components that will be used to create test cases to evaluate theperformance of the developed solvers.In Table 1 the time line of the proposed tasks is illustrated.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 23, 2016
- Source ID
- N000141613042
Entities
People
- Andrea Benigni
Organizations
- Office of Naval Research
- United States Navy
- University of South Carolina