Rapid Modular Chip-Scale Design Using an Open and Flexible Interface
Abstract
Rapid Modular Chip-Title: Rapid modular chip-scale design using an open and flexible interface Designing and fabricating a large-scale IC requires a large team effort and high cost. It also incurs a high risk of failure due to the high complexity. A modular design approach breaks down a large-scale IC to individual IPs that are independently designed and reused. In this research project, we propose a set of solutions to enable the plug-and-play of heterogeneous hardware IPs, called chiplets, on a glass interposer substrate. The 2.5D integration provides an optimal tradeoff point in terms of cost, density and performance. To enable the integration of a wide variety of chiplets of different functions and technologies, we define a common interface that governs the data exchange between chiplets. The packet-based interface is versatile enough to support the transfers of control, bulk data and sparse data. An adapter will be added to each existing IP to make a chiplet compatible with the standard interface. Adapter modules will also be designed as wrappers for legacy or COTS IPs. The approach allows us to reuse as many existing IPs as possible in building complete chip-scale systems. We will use high-speed serial link as the backbone to connect chiplets. The links will be over transmission lines on the interposer substrate. To save power, the links can be rapidly powered up and down, and they also operate in a low-power mode using static CMOS signaling for data rates in the hundreds of Mb/s range. To provide the maximum flexibility, each chiplet will operate in its own clock domain. Point-to-point links are used to pair up chiplets for highbandwidth data transfer. Multiple chiplets can all be wired to a router that provides more flexible routing options. We will use a glass interposer technology for integrating chiplets. Compared to a silicon interposer, a glass interposer is less expensive and faster to process, and it offers improved via performance. We will apply the modular design approach to existing 65nm and 40nm CMOS IPs that were designed under the DARPA ACT and UPSIDE programs. We will integrate adapters to the existing IPs and deploy them on glass interposer to demonstrate a large-scale multi-antenna signal processing system and a large-scale neuromorphic computing system.Scale Design Using an Open and Flexible Interface
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 29, 2017
- Source ID
- N000141712992
Entities
People
- Zhengya Zhang
Organizations
- Board of Regents of the University of Michigan
- Office of Naval Research
- United States Navy