Trusted Fabrication through 3D Integration Demonstration
Abstract
NCSU will demonstrate the feasibility of doing trusted chip fabrication using an untrusted CMOS source and a trusted 3D integration fab. The overall concept is to split the design into three portions and then stack them using 3DIC technologies. Two portions are fabricated in an untrusted CMOS fab, in this case Global Foundries 28 nm, while the third portion is fabricated in a trusted wiring only fab, in this case nHanced Semiconductor. The design is partitioned so that without the third portion, it is sufficiently obfuscated. The primary innovations that will be established in this effort are (1) the demonstration of split fabrication not requiring detailed fab to fab coordination, (2) new tools for design partitioning to enable this concept, and (3) establishment of new metrics to directly and indirectly measure design fabrication.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Nov 03, 2017
- Source ID
- N000141713013
Entities
People
- Paul D Franzon
Organizations
- North Carolina State University
- Office of Naval Research
- United States Navy