Towards verification-guided hardware synthesis for security
Abstract
Fabless System-on-a-Chip (SoC) designers use third-party intellectual property (3PIP) cores and in-house IP cores to design SOCs. Tr"ustworthiness of such SoCs is undermined by malicious logic (Trojans) in 3PIPs. When activated, a Trojan may result in a deadlock or" failure of the system or create a backdoor allowing the attacker to gain remote access to the system so as to leak secrets from it. The goal of this project is to develop approaches and computeraided tools to design trustworthy SoCs using untrusted 3PIPs. The approach is two fold: (i) Using verification techniques we will check if the target 3PIP satisfies security properties and their bounds"; (ii) We then use this information to synthesize the design using these untrusted 3PIPs, along with duplication, diversity, and iso""lation principles, to ensure trustworthiness. The project will investigate the formal definition of security properties, how to use""hardware verification tools to ensure the security of 3PIP, and the capabilities and limitations of such an approach. A variety of s""ecurity-driven synthesis constraints will be incorporated into a high-level synthesis framework. Informed by these capabilities, lim""itations, and synthesis constraints, the project will deliver a high-level synthesis framework,VeriSyn, which is guided by verifica""tion techniques, to ensure the trustworthiness of SoCs that are practical to deploy in security- and mission-critical systems.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 23, 2018
- Source ID
- N000141812058
Entities
People
- Jeyavijayan Rajendran
Organizations
- Office of Naval Research
- Texas Engineering Experiment Station
- United States Navy