Detection of Hardware Trojans Using Controlled Short-Term Aging
Abstract
Detection of Hardware Trojans Using Controlled Short-Term AgingThe project addresses the development of a methodology to detect hardware Trojans on processors implemented in integrated circuits (ICs) using controlled short-term aging effects. Short-term aging effects appear when a device implemented in an advanced technology node (45nm and below) is aged at a high voltage and switched from the high operating voltage to a low operating voltage. The stress on the device at the high operating voltage combined withhigher susceptibility at the lower voltage causes a temporal violation of the guard band, which results in transient errors at the circuit and system level.The proposed approach uses the stochastic temporal patterns of short-term aging as a signature for detecting hardware Trojans in an IC. Specially crafted instruction sequences are run on the processor while simultaneously modifying the operating voltage to create different short-term aging and transient error patterns. Measurements of stochastic temporal patterns from the processor (including processor states/registers and I/O lines) are then used to characterize the baseline behavior of a known-good device using a machine learning approach. When testing a possibly Trojan-infected device, measurements from the processor are probabilistically matched against the baseline response using the trained machine learning system to detect anomalies thatindicate the presence of a hardware Trojan. Moreover, when running the specially crafted test programs, the operating voltage of the processor is dynamically varied to induce additional shortterm aging effects and guard band violations. The input sequences and operating voltage modifications when testing a device form a secret key that poses a challenge for an adversarywho wishes to inject a hardware Trojan. The proposed approach uses (i) physics-based characterization of instructions, (ii) creation of test programs and operating voltage modification patterns that increases the sensitivity of the processor to hardware changes including hardware Trojans, (iii) feature extraction from processor measurements, and (iv) machine learning to characterize baseline behavior and detect anomalies in test devices. The project will include identification of instructions, test programs, and operating voltage modifications to increase sensitivity to hardware changes, feature extraction, machine learning algorithms to detect hardware modifications by characterizing baseline behavior of known-good devices and detecting anomalies in test devices to determine the presence of hardware Trojans. The proposed approach will be demonstrated using a simulation-based approach that uses real standard cells that consider short-term aging, synthesis and timing analysis tools, test benches, and optionally emulation implemented on a 16nm FPGA. We will use open-source 64- bit RISC-V and OpenSPARC processors. Several hardware Trojans will be considered to demonstrate our proposed approach.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jul 27, 2018
- Source ID
- N000141812672
Entities
People
- Farshad Khorrami
Organizations
- New York University
- Office of Naval Research
- United States Navy