Pushing the Limit of Two-Dimensional Semiconductor Transistors through van der Waals Integration
Abstract
Title: Pushing the Limit of Two-Dimensional Semiconductor Transistors through van der Waals Integration Objective:To enable optimum two-dimensional semiconductor (2DSC)/metal contact and 2DSC/dielectric interface and create high-speed transistors from 2DSCs, with unprecedented performance. Specifically, to avoid direct lithography on the delicate 2DSC surface, we will fabricate the entire gate stack and contact electrodes on a sacrificial substrate and physically transfer them onto 2DSC with minimum damage within dielectric/2DSC interface and metal/2DSC interface.Approach:To overcome previous limitations and achieve superior RF performance, here wepropose a novel approach to fabricate MoS2 transistors with sub-100 nm gate length using a metal/dielectric stack as the self-aligned top gate, and van der Waal transferred metal as the self-aligned source drain electrodes, both of which are integrated with MoS2 through a physical assembly process without damaging the gentle and dedicate two-dimensional semiconductor (2DSC) surface. In particular, the physical assembly and vdW integration of both gate stack and contact electrodes avoid any direct aggressive processes on MoS2 to prevent any integration-induced damage to the atomically thin 2DSCs, thus ensuring pristine 2DSC/dielectric interface with little trapping states and excellent channel mobility, and nearly ideal metal/semiconductor interface essentially free of interface Fermi level pinning and with minimized contact resistance. The self-aligned source-drain electrodes minimize the access resistance and parasitic capacitance and maximize the device transconductance. SOW:Key Tasks and MilestonesYear 1: Fabrication and optimization of the gate stack, source-drain contactsand the transfer process, and development of the transfer process for transistors on silicon substrate with optimized DC performance.Year 2: Integration of the gate stack, source-drain contacts with 2Dsemiconductors for creating transistors on glass substrate withminimized parasitic capacitance and optimized RF performance.Year 3: Optimization of the van der Waals integrated 2D transistors and thecreation of RF circuits.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 04, 2018
- Source ID
- N000141812707
Entities
People
- Xiangfeng Duan
Organizations
- Office of Naval Research
- United States Navy
- University of California, Los Angeles