Testbed for Experimental Validation of Security Techniques for the Protection of Circuit Integrity
Abstract
Hardware security, specifically the protection of integrated circuit intellectual property, has gained importance as adversaries have the financial and experiential means to reverse engineer and replicate a competitors IP ormodify circuits to extract critical information. One such attack is side channel characterization, which is used to extract and analyze information leaked from an integrated circuit (IC) through means such as timing, power, electromagnetic (EM) radiation, and temperature. One of the most researched side channel attacks is the use of correlated power analysis on an advanced encryption standard (AES) core. Based on multiple power traces with plaintext input, the attacker is able to determine the AES key, presenting a risk to any individual or entity that relies on the AES block for security. In addition, the end of Dennard Scaling has resulted in an increase of specialized logic to improve e?ciency, creating an increased correlation between spacial and functional activity on an IC. Therefore, investigating the power, EM, and thermal leakage channels both individually and concurrently through multi-modal sensory analysis will further enhance the security of an integrated circuit against data leakage. The testbed will provide a means to characterize the thermal, voltage/current, and electromagnetic profile of the IC for varying workload execution as well as validate obfuscation techniques developed to protect digital and analog IP.The proposed project will provide the experimental infrastructure to investigate power (including voltage and current characterization), EM, and thermal information leakage by 1) quantifying the o --chip power, EM, and thermal signatures of circuit (intellectual property cores), and 2) concurrently collect on-chip power, EM, and thermal data through an integrated sensory network to characterize and spatially map the side channels, which will then be used to analyze the increase in leaked information as compared to o --chip measurements only. The completion of this work will provide vital design insight that will 1) characterizehe information leaked through multi-modal attacks (power, EM, and temperature), and 2) provide circuit techniques and methodologies to minimize the information leakage from the circuit side-channels, with the goal of creating a more secure ICthat is resilient to side channel attacks. In addition, the testbed will provide the necessary instrumentation to validate the novel circuit techniques developed to improve the security of analog and digital electronic assets by assuring that the integrated circuitsthat are installed are not counterfeit or easily reverse engineered, which would compromise the IC and more importantly the systems that rely on these ICs. The fundamental outcome is to develop a systematic approach to analyze and obfuscate digital and analog circuit parameters that are multi-dimensional and continuous by nature. Completion of the proposed research will enable the security of circuit components, specifically mixedsignalICs, that have been for the most part ignored in the hardware security domain.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jun 13, 2019
- Source ID
- N000141912396
Entities
People
- Ioannis Savidis
Organizations
- Drexel University
- Office of Naval Research
- United States Navy