Negative Capacitance Memory Technology for Next Generation Artificial Intelligence Hardware
Abstract
Computing is changing. Over the past six decades, the semiconductor industry has been immensely successful in providing exponentially increasing computational complexity at an ever-reducing cost and energy footprint. Underlying this staggering evolution is a set of well-defined abstractionlayers, starting from robust switching devices that support a deterministic Boolean algebra to a scalable and stored program architecture, which is Turing complete, and hence capable of tackling (almost) any computational challenge. Unfortunately, this abstraction chain is being challenged as scaling continues to nanometer dimensions and also by exciting new applications that must supporta myriad of new data types. Maintaining a deterministic model ultimately puts a lower bound on the amount of energy scaling that can be obtained, set in place by fundamental physics that governs the operation and also by the variability and reliability of the underlying nanoscale devices [1,2].Within the data centric applications, one of the main bottlenecks comes from the fact that traditional computer design has separated compute block from the memory block. As a result, when todays computers need to process a very large amount of data, a significant power dissipation takes place simply in the communication between memory and logic blocks. This indicates that there is a critical need for memory technology that can be integrated with computeblocks with high density. However, the existing solutions suffer from many different issues. For example, for eFLASH, the amount of voltage needed is significant, which means that large charge pump circuits have to be used that reduces density significantly in addition to increasing power consumption. Standard DRAMs are not process compatible for integration with Si. MRAMs suffer from the need of a transistor at every cell that reduces their potential density. In general, significant improvements in the energy efficiency is possible if a memory technology can be found that can be integrated seamlessly with the compute block, can be run at a voltage that does not need charge pump circuits thereby paying no penalty in the density and with reasonable retention (seconds to years depending on the application).Our objective in this program is to exploit the physics of recently discovered physics of negative capacitance in ferroelectric materials, combined with material synthesis and device design to develop memory technologies that can overcome the memory bottleneck as described in the above.Specifically, we plan to develop non-volatile memory technology that consists of a single FIN FINET, thereby obtaining the highest density possible, with 100 nanosecond program and erase speed (thereby exceeding the latency of todays 3D X-point by 100X times) at the same endurance as eFLASH technology in a back end of the line compatible process.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 31, 2020
- Source ID
- N000142012775
Entities
People
- Sayeef Salahuddin
Organizations
- Office of Naval Research
- United States Navy
- University of California Regents