Three Dimensionally Integrated XNOR Logic Circuits
Abstract
This proposal is to develop material synthesis and optimization for high mobility poly-crystalline transistors using metal induced phase crystallization below 550C. These transistors could lead to significant boost in the READ speed of the developed content addressable memory (CAM) cells.The use of Si channel has the advantage of using the same HZO surface chemistry that has been developed for standard crystalline Si transistors over the last few years. We note here that the potential use of such high mobility transistors is substantial and goes well beyond FerroElectric Field Effect Transistor application. It could potentially provide a viable method for a BEOLtransistor technology. If the annealing temperature requirement can be brought down below 450C, it will be compatible with the most advanced nodes. Even at 550C, it is compatible with 65 nm node. Many data-centric applications could highly benefit from compute-in -memory functions performed in high density, BEOL integrated memory, even with an underlying 65 nm node ALU. In other words, for many modern, data-centric work loads, having access to the mostadvanced node is not the critical challenge, rather physical distance between memory and logic circuit blocks pose the most dominant bottleneck -often known as the memory wall. In this context, a high performance BEOL transistor technology has the exciting potential to provide substantial boost by bringing a large portion of the driving circuitry at the back end, much closer to the memory itself.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Oct 19, 2020
- Source ID
- N000142012853
Entities
People
- Sayeef Salahuddin
Organizations
- Office of Naval Research
- United States Navy
- University of California Regents