Chip Fabrication and Instrumentation for Hardware Trojan Detection
Abstract
This DURIP project will build on an on-going ONR-funded research project, in which New York University (NYU) in collaboration with Karlsruhe Institute of Technology (KIT) is developing methodologies to detect hardware Trojans based on the physical phenomenon of short-term aging. The efficacy of short-term aging based hardware Trojan detection has been demonstratedvia high-fidelity physics-based simulation studies on several integrated circuits (ICs) with several types of hardware Trojans. The simulation studies considered significant amounts of IC-to-IC and on-chip variations through stochastic perturbations injected into the simulation studies. Parameters for the stochastic variations are picked to cover even the higher stochastic variations expected innewer technology nodes such as 28nm and smaller. To validate the efficacy of the proposed, this DURIP project seeks to demonstrate hardware Trojan detection in actual physical ICs. For this purpose, this DURIP project is proposing a novel experimental testbed consisting of: A specifically designed IC that contains Trojan-free and Trojan-infected variants of multiple circuits (e.g., cryptographic accelerators and micrcontrollers). This IC will be the device under test (DUT) for evaluation of the efficacy and accuracy of the hardware short-term aging based Trojan detection methods. We envision 3mm3mm ICs fabricated in the 28nm process Global Foundries. These ICs will have Trojan-free and Trojan-infected variants of multiple circuits. These will be used as DUTs to validate the Trojan detection methodology. An FPGA-based interface module to apply clock signal and inputs to the DUT (the fabricatedIC) and collect outputs. This will have a Xilinx Virtex UltraScale+ HBM VCU128 FPGA to interface with the DUT (to apply clock and inputs, collect outputs after precise amounts of time measured as number of cycles). A fast switching programmable power supply for precise application of supply voltage changes to the DUT. Specifically, we will use a Tektronix Keithley 2281S-20-6 Precision DC Supply/Battery Simulator, 20V/6A. This unit will apply patterns of supply voltages to the DUT to induce controllable and repeatable levels of short-term aging. Finally, a data analysis software module on a host computer for machine learning based device evaluation and anomaly detection (i.e., detection of hardware Trojans). This testbed is a vital resource in the physical validation of the proposed hardware Trojan detection methodology. The primary focus in the development and integration of the testbed is to validate the NYU-KIT hardware Trojan detection methodology. However, this testbed will be a valuable resource for evaluating and validating other hardware Trojan detection techniques developed by NYU and the hardware security researchers outside of NYU (e.g., fuzzing-based, VLSI testing-based, and power monitoring based techniques). The testbed will be a unique experimental facility for the hardware security community by providing access to (i) physical ICs with Trojanfree and Trojan-infected variants of circuits ranging from moderate-sized cryptographic circuits tocomplex microprocessors plus (ii) a generic FPGA-based interface to interrogate and test these ICs for Trojans according to their detection method.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- May 05, 2021
- Source ID
- N000142112390
Entities
People
- Farshad Khorrami
Organizations
- New York University
- Office of Naval Research
- United States Navy