SAIPA: Security Aware Interposer Design for Heterogeneous Packaging

Abstract

With the rapidly rising cost of maintaining high-end foundries, the modern semiconductor industry has predominantly shifted to a horizontal business model, whereby integrated circuits (ICs) at advanced technology nodes are fabricated offshore. While this strategymakes sense from an economical perspective, it has raised serious concerns for semiconductor intellectual property (IP) protection.In order to fabricate ICs, a design house provides the entire design to the foundry (in the form of a layout/GDSII file), and in most cases, even the complete test patterns and responses needed to verify the chip functionality at post-fabrication. It is trivial for the foundry to extract the complete netlist of the design from the GDSII file. As a result, the foundry has complete access to the entire design, potentially leading to overproduction, cloning, IP infringement, and even hardware Trojan insertion. Such concerns are especially alarming for Department of Defense (DOD). In this project, wepropose SAIPA, a security-aware interposer design for heterogeneous packaging, to explore the vulnerabilities of interposer-based fabrication model and formulate various approaches to makeuse of the interposer features to ensure the security of the 2.5D fabrication model. Such an approach is of high importance to DOD because of the newly established zero trust assumption in building electronic devices and systems. SAIPA aims to assess the securityvulnerabilities in an interposer-based split fabrication model and develop countermeasures to exponentially increase the complexityof solving the unknown connections through an interposer layer. SAIPA allows secure fabrication of electronic systems, while each die integrated in the 2.5 or 3D packaging may not necessarily be trusted. Further, DODs need to integrate a number of different diesinto one package (digital, analog, memory, etc), makes SAIPA a necessity to establish security.

Document Details

Document Type
DoD Grant Award
Publication Date
May 05, 2021
Source ID
N000142112513

Entities

People

  • Navid Asadi Zanjani

Organizations

  • Office of Naval Research
  • United States Navy
  • University of Florida

Tags

Readers

  • Cybersecurity.
  • Economics
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics