Integrated CryoElectronics TestBed for Modeling and Characterization of a High-Speed Superconducting and cryo-CMOS Circuits
Abstract
The objective of this proposal is to acquire the test and measurement equipment necessary to comprehensively investigate the cryogenic superconducting technology circuits supported by current ONR grant awards (#N00014-18-1-2254 and #N00014-20-1-2109) and significantly impact future research at WSU in cryoelectronic circuits and systems. The acquired equipment will establish a new state-of-the-art cryoelectronics laboratory at the School of Electrical Engineering and Computer Science (EECS) at Washington State University (WSU).The proposed testbed will enable the design and validation of high data-rate communication links utilizing cryogenic and room-temperature digital signal processing (DSP) solutions. The custom-developed prototypes employing complementary metal-oxide semiconductors (CMOS) technology will enable bias homogenization of the two-terminal Josephson Junction (JJ) using artificial-intelligence-based optimization methods between the cryoelectronics and the room temperaturethat limits ability for fast readouts with reduced pin count. This DURIP will thus enable several DoD applications including sensing, communication systems, and quantuminformation processing.Further, the developed techniques are being validated currently through Hypres Inc. in New York that currently involves cross-country travel and resource planning. This cryogenic test capability will become even more critical in the follow-on efforts where functionality proved currently on field-programmable gate arrays and software is migrated onto the cryo-CMOS chip after modeling and validating transient parameters and will enable versatile and modular design for variable temperature testing on Hybrid-Temperature Heterogeneous Systems technology experiments.The versatility of the proposed cryogenic testbed facility also makes it a very powerful platform to develop and test components needed for interfacing superconducting electronics and quantum integrated circuits with room temperature systems. In particular, it will enable modeling and characterization of energy-efficient and high-speed links using cryo-CMOS between submillikelvin temperatures up to 40K. Besides, it will harness the power of future quantum technologies that will require a hybrid approach leveraging the intrinsic strengths of different platforms: superconducting gates are especially fast processors and are adept at interfacing with classical electronics, photonic qubits allow for coherent quantum information to be transmitted over long distances through an optical fiber, and cold atoms provide the potential for incredibly long coherence times opening up the possibilities for quantum memory.The proposed infrastructure will greatly enhance the education of a broad spectrum ofstudents leveraging the PI s expertise in analog / mixed-signal processing, millimeter-wave communication, and fundamental quantum physics at cryoelectronic temperatures. The PIs intend to extend the hands-on learning experience to the projects graduate students as well as a larger group through multiple undergraduate and graduate courses. The PIs also plan to involve undergraduate students in research projects utilizing the proposed laboratory.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 05, 2021
- Source ID
- N000142112684
Entities
People
- Subhanshu Gupta
Organizations
- Office of Naval Research
- United States Navy
- Washington State University