FPGA-Based CHiL-Based RT Simulator
Abstract
A Real-Time (RT) Controller-Hardware-in-the-Loop (CHiL) simulation platform capable of evaluating the fault behavior and protective system implementations for networked Power Electronic Converter (PEC)-based DC distribution systems requires much smaller simulati on time-steps than can be achieved with commercially available Hardware-in-the-Loop (HiL) hardware systems. Time-step resolution o f less than 100nsec is required to faithfully reproduce dynamic responses and commonmode behavior associated with multiple PECs tha t are interconnected by a cabled electrical network subject to sudden inception line-to-line and line-to-ground short circuits. Thi s proposed equipment will enable implementation of RT CHiL simulations in a commercially sustainable, adaptable and flexible Field Programmable Gate Array (PFGA)-based hardware platform. This equipment expands the capability of the proposers HiL/CHiL laborator y to perform RT simulation of fault characterization on shipboard multi-zonal shipboard electrical systems. The RT simulation capab ility will be expanded through use of FlexRIO FPGA plug-in modules that communicate via peer-to-peer streaming, over a PCI Express (PXIe) backplane implemented in a National Instruments PXIe-1095 chassis. The RT simulations utilize a custom Latency-Based Linear Multistep Compound (LB-LMC) transient simulation solver for power electronics and generation systems with nonlinear, multi-physics elements. The proposer has already demonstrated RT simulation of PECs subject to sudden short-circuit fault inception on a standa lone FlexRIO FPGA system, achieving 50nsec resolution. Simulation models are programmed using LabView with custom developed LB-LMC component models for PECs, distribution elements and switches, suitable for high-resolution RT simulation execution of short circu it fault responses of networked PECs. Modular implementation of multi-FPGA based RT CHiL simulations enables evaluation of Fault D etection Isolation and Reconfiguration (FDIR) control sequences implemented with either PEC-based or Breaker-based shipboard electr ical architectures. Additionally, with the proposed equipment, firmware associated with FDIR controls can be implemented on FlexRI O modules, dedicated to this purpose, to evaluate protection schemes, system recoverability and to derive timing and latency requir ements for final hardware implementations. The system will include sufficient I/O to enable co-simulation with the proposers OPAL- RT system and remote co-simulations with much larger HiL/CHiL systems at collaborator institutions, which implement power conversi on controls, distributed generation, electrical grids and shipboard intra-zonal AC/DC distribution systems. This equipment is found ational and critical to the proposers research on the evaluation of survivability capability of Navy ship and base electrical netw orks made up of communication networked PECs and Fault Isolating Devices (FIDs).
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Nov 16, 2021
- Source ID
- N000142212000
Entities
People
- Robert Cuzner
Organizations
- Office of Naval Research
- United States Navy
- University of Wisconsin System