Temporal (Sequential) Locking of Mixed-Signal and Digital Circuit Intellectual Property
Abstract
The increasing inclusion of third-party IP and the use of third-party IC fabrication facilities has allowed for advances in the comp,lexity and functionality of IC designs, but has also introduced untrusted entities into the IC design flow. The presence of untruste,d parties raises concerns over IP theft, counterfeiting and overproduction of ICs, and the insertion of harmful circuit modification,s (hardware Trojans). An area of research that addresses the security risks of IP theft, IC counterfeiting, IC overproduction, and h,ardware Trojan insertion is logic locking/encryption [213]. However, the satisfiability (SAT) based attack presented in [14] circum,vents the security provided by logic locking and, therefore, requires the development of novel measures to defend against the wide v,ariety of threats facing ICs. To reduce the susceptibility of an IC to both structural and oracle guided attacks, sequential logic l,ocking is proposed as means to secure the IC. As opposed to combinational logic locking, sequential logic locking requires a key seq,uence to activate an IC. As the activated IC is in a different state space than the locked IC, oracle guided attacks do not provide,information about the activation key sequence of a sequentially locked circuit.While the transition information is secure, the secur,ity of sequential logic locking is largely dependent on the choice of the finite-state machine (FSM) to decrypt. Whether the logical, depth of the FSM is shallow, or the probability of transition to unique states is low, the logical structure of the FSM significant,ly impacts the security of sequential logic locking. In addition, the threat of IP theft is often unaffected by sequential logic loc,king since the logic cone is able to be reverse engineered by an adversary. Logic cone modifications reduce the susceptibility to IP, theft, but structural attacks [15, 16] prevent significant gains in security from being realized. The proposed work introduces a no,vel means of increasing the security of a sequentially logic locked circuit. The completion of this work will 1) develop metrics tha,t evaluate the strength of a sequentially locked circuit, which will allow for the efficient and secure insertion of locking states,, 2) develop the ability to expand the state space an adversary must search, 3) develop algorithms and methodologies that modify the,logic cone of a circuit to prevent structural vulnerabilities and improve execution time over current techniques, and 4) provide exp,erimentally validated functional testing of a sequentially locked IC.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 14, 2022
- Source ID
- N000142212071
Entities
People
- Ioannis Savidis
Organizations
- Drexel University
- Office of Naval Research
- United States Navy