COSIMILA: Accelerating System-Level Co-simulation using ILA (Instruction-Level Abstraction) Models
Abstract
Abstract: Approved for Public ReleaseCOSIMILA: Accelerating System-Level Co-simulation using ILA (Instruction-Level Abstraction) Mod,elsPIs: Sharad Malik and Aarti Gupta, Princeton UniversityThis project aims to accelerate system-level co-simulation for systems-on-,chip (SoCs). SoCs are ubiquitous in computing and communication infrastructure, which provide the technology bedrock of critical sys,tems in modern society, including the defense systems of relevance to the US Navy. Ensuring correctness, safety, and security of SoC, designs is of tremendous importance. The proposed work for system co-simulation of SoCs will have impact in reducing the costs for,SoC design validation, improving the design quality by finding bugs in a timely manner, and enhancing the safety of mission equipmen,t.There are three distinct strategies to improve co-simulation performance -- process each simulation event faster, reduce the numbe,r of events, and raise the level of abstraction of simulation models. Our proposed approach follows the third strategy, where co-sim,ulation is performed at the instruction/architecture level, rather than the Register-transfer Level (RTL) by using architecture-leve,l models for heterogeneous software-programmed/controlled hardware components such as processors, accelerators, and peripheral devic,es. Specifically, we will use the recently proposed Instruction-Level Abstraction (ILA) abstraction for processors and accelerators., We will consider both manually written ILA models, as well as those auto-extracted from RTL.The goal of the proposed research is to, accelerate system-level system-on-chip (SoC) co- simulation by >100X over RTL-based co-simulation for manually-written ILA model-ba,sed co- simulation, and by 10-50X using ILA models auto-extracted from RTL. This enables: (i) checking the correctness of the softwa,re as well as the hardware components (accelerators/devices) through their software-driven invocations, and (ii) early software deve,lopment in parallelwith hardware development.Current software-hardware co-simulation practice uses either low-level RTL models for h,ardware components, or high-level abstract hardware models in SystemC/C++. Using low-level RTL models provides for high-assurance of, correctness and low-cost of co-simulation development through use of RTL models, but at the cost of co-simulation speed due to the,low- level RTL model. Using high-level abstract models requires additional cost for developing these SystemC/C++ models and results,in loss of assurance of correctness of these high-level models relative to the RTL implementation, but provides the benefit of highe,r simulation speed. The proposed approach of using ILA models for hardware components directly addresses this tradeoff by providing,the speed advantages of abstraction with sound ILA models verified using existing ILA verification flows (developed as part of the P,OSH program) or correct-by-construction auto- extracted ILA models developed as part of the proposed research. The use of ILA models, for hardware components accomplishes the above-mentioned advantages as follows. The ILA model provides the highest-level level of a,bstraction possible for co-simulation since it retains only the software-visible state. This provides for the highest-possible speed,up in co-simulation. Further, the ILA methodology provides for formal and simulation-based verification of ILA models against RTL im,plementations, and thus the co-simulation has the advantage of using sound hardware abstractions. In addition, auto-extraction provi,des for correct-by-construction ILA models.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Mar 05, 2022
- Source ID
- N000142212168
Entities
People
- Sharad Malik
Organizations
- Office of Naval Research
- Trustees of Princeton University
- United States Navy