Buffer Layer Mediated van der Waals Integration of Contacts and Dielectrics on Two-Dimensional Semic
Abstract
Two-dimensional semiconductors (2DSCs) have attracted tremendous interest as an atomically thin channel for the continued transistor, scaling. To construct a functional transistor from the 2DSCs requires the integration of the 2DSCs with other critical device compo,nents, including source-drain electrodes, gate dielectrics and gate electrode, with minimum damage to the atomic lattice and electro,nic structure of the 2DSCs, which is a non-trivial challenge. Conventional electronic manufacturing, including lithography, vacuum d,eposition, and plasma etching processes, usually involve aggressive chemical processes that induce undesired structural disorders in, 2DSCs and seriously degrade their electronic properties. To robustly probe the performance limits of 2DSCs and capture their intrin,sic merits in functional devices face considerable challenges in material integration and device fabrication. In particular, it is e,ssential to retain the pristine contact interfaces and dielectric interfaces with minimum interfacial trapping states.This project a,ims to exploit a removable buffer layer on 2DSCs to prevent direct impingement by hot atoms during physical vapor deposition of meta,l electrodes. Once the deposition is completed, the buffer layer is vaporized at a moderate temperature, allowing the deposited meta,l thin film electrodes to naturally relax onto the 2DSC surface to form bond-free and defect-free VDW interfaces. We will explore a,series of buffer layers and conduct systematic structural and spectroscopic studies to investigate how the exact buffer layer, proce,ssing temperature and pressure could mitigate the deposition induced damage. We will further use the proposed approach to integrate,a series of metals of different work functions on 2DSCs, conducting fundamental transport studies to determine barrier height, Fermi, level pinning effect and Schottky-Mott rule. We will further adapt this approach for damage-free integration of high-k dielectric o,n 2DSCs with minimum interfacial trapping states. With the optimization of contact and dielectric interface, we will further constru,ct 2DSC transistors with variable channel lengths to systematically probe the contact resistance, on-state current density, mobility, and subthreshold swing, and investigate how such performance metrics depend on the integration process and scale with channel lengt,h, channel thickness and dielectric thickness.The proposed studies address the fundamental technical challenges in integrating 2DSCs, in high-performance devices, and represent the essential steps for pushing and probing the fundamental performance limits of 2D tra,nsistors. A close integration of the microstructural imaging, spectroscopic characterizations and capacitance and electrical transpo,rt studies will help develop a fundamental understanding of the critical factors governing the contact barrier, contact resistance,,carrier densi,ltaneously optimized contact and dielectric interfaces are essential for probing the ultimate scaling limit of 2DSCs and critically,gauging their potential for the continued transistor scaling down to sub-10 nm channel length regime. Successful execution of the pr,oposed effort will define a new pathway to high performance 2D electronics and establish the intellectual underpinning for adopting,them in semiconductor industry. It could open up many exciting opportunities in 2DSC-based electronic devices for various naval appl,ications, including low-power electronics, advanced military imaging technology, novel sensors for chemical warfare detection.?Appro,ved for Public Release?
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Aug 05, 2022
- Source ID
- N000142212631
Entities
People
- Xiangfeng Duan
Organizations
- Office of Naval Research
- United States Navy
- University of California, Los Angeles