1D Coherent Conformal Epitaxy for High-Performance 2D Electronics
Abstract
Approved for Public Release: Monolayer of transition metal dichalcogenides (TMDs), featuring atomic thinness, dangling-bond-free sur,face, and electrical and chemical diversity, promise to facilitate further miniaturization and thinning of high-performance electric,al devices, including field effect transistors (FETs). Over the past decade, researchers have continued to make progress for solving, key material challenges including growth of high-quality wafer-scale TMDs, improving contact resistance, finding high-k dielectrics,, and developing flexible patterning techniques. These have led to significant advances and discoveries bearing great promises to ad,dress future challenges faced by the semiconductor community. The main aim of this proposal is to develop one-dimensional (1D) defec,t-free coherent heterojunctions formed between two dissimilar two-dimensional (2D) crystals of TMDs for high performance electrical,and optoelectronic devices. For this, we propose to develop a novel synthetic approach of 1D coherent conformal epitaxy (1D-CCE), wh,ich can be applied generally to a variety of TMD monolayers that are pre-patterned with micro- and nano-scale features. Once develop,ed, 1D-CCE will be utilized to fabricate wafer-scale arrays of defect-free, single-crystalline TMD heterostructures. They will be us,ed to fabricate high-performance FETs, where the structure and electrical properties, including contact resistance at the 1D contact,s are systematically investigated and optimized using state-of-the-art characterization methods. Our proposal addresses key needs wi,th ONR relevance by providing a powerful new approach toward developing ultrathin electronic devices with extreme performances curre,ntly not available. In particular, the success of this proposed work will unlock the full potential of atomically thin materials by,developing 1D edge contacts with a low intrinsic volume that are (i) scalable with low contact resistances, (ii) chemically and ther,mally stable, and (iii) versatile toward use with different 2D materials. Critical to this goal is the design and fabrication of coh,erent semiconductor-metal junctions that are free of defects in a way that is applicable to the batch fabrication of FETs. Compared,with the conventional approach of top contacts, which is extensively investigated, the edge contacts are not well explored, and henc,e underdeveloped. Our proposed 1D-CCE will thus lead to the formation of ideal edge contacts that can result in highly improved devi,ce performance with low contact resistance, low-power dissipation, and high on-current. The proposed process will also be compatible, with wafer-scale batch fabrication, and this could lead to the development of high-speed, low-power computing with extremely small,device volume.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Oct 07, 2022
- Source ID
- N000142212841
Entities
People
- Jiwoong Park
Organizations
- Office of Naval Research
- United States Navy
- University of Chicago