Next Generation Neuromorphic Chips based on Compute-in-memory Architecture with Bulk Switching Resistive Memory Arrays
Abstract
Next Generation Neuromorphic Chips based on Compute-in-memory Architecture with Bulk Switching Resistive Memory ArraysPublicly Releasable AbstractIn this proposal, we request funding to cover manufacturing and testing costs of a next-generation neuromorphic chip based on CMOS-RRAM integration. This new chip will integrate high density RRAM arrays at the top of CMOS neuron circuits to perform training and inference with high throughput and low energy consumption in resource limited settings. Our current ONR grant on developing computational models of hippocampus microcircuits based on brain inspired next generation deep learning has led to exciting results in the areas of device technologies and neuromorphic architectures. We demonstrated that CMOS-RRAM based neurosynaptic core with dynamically reconfigurable dataflow that can achieve an extremely high energy efficiency (74 TMACS/W). We developed a new bulk switching resistive memory technology that can enable implementation of online learning in the hardware with substantially greater energy efficiency and bandwidth than other deep learning/AI approaches. This new memory technology will be integrated with massively parallel distributed and hierarchically structured neuromorphic architecture to fundamentally advance the state-of-the-art neuromorphicchips. In our ONR project we aim to develop this next generation neuromorphic chips, which will provide (i) capability for persistent online learning through continuous weight updates; and (ii) efficient implementation in massively parallel distributed and hierarchically structured CMOS architecture, operating entirely on local variables. If successful, this next generation neuromorphic chip will offer tremendous potential in overcoming mounting challenges in the natural intelligence and persistent autonomy of unmanned fleet/swarm Navy operations in environments where direct human participation would pose great risk to warfighter health/survival and/or to mission effectiveness. Requested funding will be used to manufacture chips at CMOS foundries, to integrate bulk RRAM devices atthe top of CMOS chips at UC San Diego Nanofabrication facility, and to acquire test equipment needed to test high density memory arrays. To-date, we have demonstrated proof-of-concepts for individual components of this project. However, integration of neuromorphic CMOS circuits with bulk switching RRAM technology requires dedicated funding for covering chip manufacturing costs. In addition, lack of high speed and low noise electrical characterization equipment limits our abilities to conduct accurate longitudinal measurements with precise control over large numbers of RRAM elements, especially the new bulk switching devices that have a wider dynamic range of operation. The requested funds in this DURIP proposal will provide the complete test setup and manufacturing resources necessary to build the next generation neuromorphic chips with online learning capability.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 12, 2023
- Source ID
- N000142312163
Entities
People
- Duygu Kuzum
Organizations
- Office of Naval Research
- United States Navy
- University of California, San Diego