Multi-resolution, multi-precision FFT Accelerator in a 3D NAND Flash memory
Abstract
A direct sampling radio frequency (RF) architecture has gained high interest in today s multi-channel digital receivers in defense applications, for example, advancing the capability of electronic warfare (EW), intelligence, surveillance, and reconnaissance (ISR). It benefits from a simplified RF front-end, direct digitization of RF signals, sufficient dynamic range, small form factors, and reduced cost. Fast Fourier Transform (FFT) is at the heart of the technology portfolio in digital signal processing of direct sampling RF receivers. The demand for a higher sampling rate in direct sampling RF receivers has increased the demand for a giga sampling, multi-channel, multi-resolution, multi-precision FFT accelerator. State-of-the-art FFT accelerators for today s ultra-wideband (or direct sampling) RF receivers have been implemented by FPGAs, GPUs, or CPUs, promising high-performance processing capabilities in real-time. Among these processing elements, FPGAs are promising solutions due to the high degree of flexibility, full compatibility with existing digital signal processing (DSP) platforms, and reasonable cost. FPGAs are promising solutions for real-time FFT computation, but high-power consumption is undesirable for platforms with size, weight, and power (SWaP) constraints. Better SWaP has been achieved by adopting an application specific integrated circuit (ASIC) technology in FFT accelerators, but their utilization is limited to specific applications due to the limitation in throughput. ASIC approaches are a clear-cut solution for low-resolution with giga sampling throughputs or high-resolution with mega sampling throughputs for energy efficient applications. However, ASIC solutionsstill have limitations in achieving real-time, giga sampling, high-resolution FFT computing capability for ultra-wideband RF antenna receivers. We propose a giga sampling, multi-resolution, multi-precision FFT accelerator based on the true in-memory computing capability in a3-dimensional NAND flash memory, enabling the quick achievement to the high technology readiness level (TRL), i.e., TRL > 4. In our effort, NAND flash memory will be employed as a vector matrix computation core and a twiddle factor storage for large-scale FFT computation. NAND flash memory is strategically chosen to maximize TRL, accelerating integration into existing DSP units for Navy s EW- or ISR-related platforms and making our accelerator compatible with conventional processors or other spectrum warfare accelerators with no or minimum modification. All our proposed efforts will be demonstrated on hardware platforms using a commercial off-the-shelf (COTS) NAND flash memory and silicon-based single-chip solution. To save the development cost and time, a large-scale FFT simulator will be developed as the first step using a compact Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) model developedby the team. A prototype single-chip solution will be designed to be reconfigurable both in resolution and precision. The ASIC willbe fabricated in an advanced silicon process. The proposed FFT accelerator will pave the way for an energy efficient, compact, single chip solution for real-time, giga sampling, multi-resolution, multi-precision FFT computation in ultra-wideband RF antenna receivers. It will offer a power reduction of several orders of magnitude (x1000) as well as size and mass benefits of several orders of magnitude (x1000) from integrating several previously discrete functions into a single ASIC. Its flexible design in resolution and precision will enable the commissioning of the proposed FFT accelerator into multiple use cases beyond Navy, for example, real-time spectrum analysis missions with SWaP constraints in NASA or Department of Energy.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Mar 08, 2024
- Source ID
- N000142412186
Entities
People
- Sungho Kim
Organizations
- Office of Naval Research
- United States Navy
- University of Rhode Island