New Trust Approach Demonstration

Abstract

This project funds a program of research to develop, and demonstrate the next generation, technology-driven approach to microelectronics trust and assurance, to include SOTA microelectronics, to ensure continued access to SOTA microelectronic technologies, while maintaining the required level of trust in all environments. DoD’s ability to access commercial technology for its custom secure, trusted and assured needs is diminishing as SOTA suppliers become fewer and more focused on serving the global commercial market. DoD’s technology needs are broad, and relying on a single source supplier is not feasible. Alternative, advanced manufacturing methods, technologies, and design tools are needed to produce secure, trusted and assured SOTA parts from commercial sources and to preserve access to these advanced nodes while protecting DoD and Defense Industrial Base IP from exploitation. It also is intended to dramatically improve the capabilities of the JFAC with regard to verification and validation of microelectronics trust and assurance. This program of research will demonstrate innovative design, manufacturing, imaging, tagging, and control and assessment approaches for protecting DoD’s microelectronics supply chain and intellectual property (IP), including alternatives for trusted, strategic radiation-hardened electronics in advanced technology nodes for next-generation strategic systems, obfuscation and disaggregation technologies, and other assurance mitigations. It will develop advanced imaging technologies and forensics, Design for Trust techniques, active hardware trust control, electronic component markers, and a data and analysis capability to enable auditing and independent verification and validation of commercial designs. It also demonstrates, and implements concepts for the cost-effective production of custom microelectronics in low volumes and protection of sensitive IP from exploitation. Technologies that provide trust and assurance in a broad range of trusted and commercial environments can mitigate the risks associated with sole-source suppliers, and increase the Government’s ability to leverage commercial capabilities. The suite of demonstrated technologies, e.g., alternative manufacturing methods and design tools, would enable DoD to obfuscate the purpose of sensitive devices, verify their origin and function, and protect sensitive IP from exploitation even while using the global supply chain for most hardware. In cases where the risk involved precludes that level of commercial collaboration, low-volume manufacturing technologies demonstrated under this project would permit DoD to more cheaply produce low volumes of sensitive microelectronics in trusted environments. The project would also support using a repository of third-party IP to expedite circuit design and transition promising technologies to use. This project will also support the following: 1) secure design environments, including high-performance computation environments, for collaboration across the U.S. Government and with private innovators to jointly conduct research on areas such as secure verification of hardware; 2) electronic design automation (EDA) tools and cell libraries; 3) persistent expertise to engage with innovation teams and sponsors to develop business models, IP articles and licensing agreements, architectures, and standards that align with U.S. Government interests in assurance and security strategy; and 4) assured field programmable gate array (FPGA) development and product demonstration for commercial FPGAs.

Document Details

• Document Type: Project
• Publication Date: Oct 01, 2018
• Source ID: P809_0605294D8Z_5_0400_PB_2018

Tags

Readers

• Cybersecurity.
• Defense Technology Research and Development.
• Integrated Circuit Design and Technology.

Technology Areas

• Microelectronics