New Trust Approach

Abstract

This project funds a technology demonstration and transition program to develop, demonstrate and pilot the next generation, technology-driven approach to microelectronics trust, to ensure continued access to leading-edge microelectronic technologies while maintaining the required level of trust in all environments. DoD’s ability to access commercial technology for its custom trusted needs is diminishing as leading-edge suppliers become fewer and more focused on serving the global commercial market. DoD’s technology needs are broad, and relying on a single source supplier is not feasible. Alternative, advanced manufacturing methods, technologies, and design tools are needed to produce trusted state-of-the-art (SOTA) parts from untrusted sources and to preserve access to these advanced nodes while protecting DoD and Defense Industrial Base IP from exploitation. It also is intended to dramatically improve the capabilities of the Joint Federated Assurance Center (JFAC) with regard to verification and validation of microelectronics trust. This program will develop innovative design, manufacturing, imaging, tagging, and control and assessment approaches for protecting DoD’s microelectronics supply chain and IP. It develops advanced imaging technologies and forensics, Design for Trust techniques, active hardware trust control, electronic component markers, and a data and analysis capability to enable auditing and independent verification and validation of commercial designs. It also develops, demonstrates, and implements concepts for the cost-effective production of custom microelectronics in low volumes and protection of sensitive Internet Protocol (IP) from exploitation. Technologies that assure trust in a broad range of trusted and non-trusted environments can mitigate the risks associated with sole-source suppliers, allow DoD to quickly respond to the loss of a Trusted Foundry, and increase Government’s ability to leverage commercial capabilities. The suite of developed technologies will enable DoD to obfuscate the purpose of sensitive devices, verify their origin and function, and protect sensitive IP from exploitation even while using the global supply chain for most hardware. In cases where the risk involved precludes that level of commercial collaboration, low-volume manufacturing technologies developed under this project would permit DoD to more cheaply produce low volumes of sensitive microelectronics in trusted environments. The project would also support using a repository of third-party IP to expedite circuit design and transition promising technologies to use.

Document Details

• Document Type: Project
• Publication Date: Oct 01, 2017
• Source ID: P839_0605140D8Z_5_0400_PB_2017

Tags

Readers

• Cybersecurity.
• Integrated Circuit Design and Technology.

Technology Areas

• Microelectronics