12nm InP-based CMOS for Extreme-Speed Logic
Abstract
Building on UCSB s record InP-based NMOS technology, in this program we seek to develop a l 2nm (physical) gate length InP-based CMOS technology for record-speed, moderate-scale logic. The key technology risk to retire is the PMOS gate dielectric. The DOD seeks extremely fast, moderate-scale logic res. 130nm InP HBT ICs are the fastest logic technology, but without a complementary device, these ICs dissipate power even when not switching, dissipating high power in medium to large ICs. FETs in commercial Si VLSI are designed to balance speed and standby power. A custom InP-based CMOS technology will be markedly faster, both because of high III-V carrier velocities and because the FET will be designed for highest speed, not densest integration. This program seeks to develop such a technology. Extreme speed InP-based CMOS is now feasible because of a decade of worldwide development of InP-based NMOS FETs, targeting VLSI at the 7nm node (~15nm Lg). In(Ga)As gives higher on-currents and smaller input capacitances; in larger interconnect-capacitance dominated ICs, the high on-currents provide higher speed than Si, while in smaller FET-capacitance-dominated ICs, the smaller FET capacitances provide further speed benefit. In present III-V NMOS technology, the gate dielectrics are extremely high quality, and FETs to 12nm Lg can be quickly built; a low-parasitic self-aligned III-V MOSFET should have > 1 THz current-gain cutoff frequency. A fast III-V CMOS technology would require in addition a fast III-V P-FET, and this must be integrated with the NMOS device. Recent data suggests that III-V PMOS may be feasible. Unpublished data on InGaAs PMOS capacitors (Stemmer group, UCSB), with HfO2 dielectric show good characteristics, but further PMOS gate dielectric development is needed. As in modern Si finFETs, in III-V, the PFET can be as fast as the N-FET. The key is to change from the [100] to the [011] orientation. This gives very high hole velocities in ultra-thin channels. The III-V P-FET should have ~1 THz current-gain cutoff frequency. In Si finFETs, the fin surfaces are naturally [011]; for III-V CMOS, we will use planar FETs on [011] wafers. The program statement of work is as follows: (1) III-V P-FET DC development, focusing on the gate dielectric and DC test structures. (2) Demonstrate high-current ill-V P-FET at 12nm Lg, focusing on DC parameters and using a fast 4-day non-self-aligned process with 12nm Lg , but with high parasitics and low current-gain cutoff frequencies. (3) Fabricate self-aligned (fast) PMOS and NMOS FETs, on different wafers, measuring DC parameters and bandwidth, and ( 4)integrate PMOS and NMOS on a common wafer, demonstrate a small-scale record-speed digital test ICs.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jan 12, 2017
- Source ID
- W911NF1610033
Entities
People
- Mark J. W. Rodwell
Organizations
- Army Contracting Command
- Office of the Secretary of Defense
- University of California, Santa Barbara