An On-Chip Thermal Sensing Method to Detect Malicious Integrated Circuits
Abstract
A major challenge associated with the security of chips is that design companies are continuing to lose control over manufacturing operations because the high-volume fabrication of chips with complementary metal-oxide semiconductor (CMOS) technologies is being transferred to foundries of other companies around the globe. This shift has led to critical security concerns because malicious circuits can be inserted during the fabrication process, which calls for novel methods to resourcefully verify every chip received from a manufacturer. Diverse approaches are emerging to detect harmful circuits that can leak information, manipulate information, or deactivate a chip. Many of these techniques involve measurements of power dissipation with external test equipment to identify the presence of maliciously inserted circuits. The primary objective of this research is to circumvent the need and cost of external measurement equipment with a proposed on-chip detection system, which will also enable periodic checking throughout the lifetime of a chip. A transformative methodology will be created in which small on-chip temperature sensors throughout the chip are used to sense power dissipation in nearby circuits, thereby revealing activity of any circuits that were added without consent of designers. Auxiliary on-chip circuits will be devised to process the sensor output signals and to convert the information into the digital domain for further analysis. A test platform will be developed to permit statistical analysis and to formulate detection algorithms such that they can be realized on the chip in the future. To demonstrate the concepts, prototype chips with the complete detection system will be fabricated and experimentally evaluated together with on-chip digital and analog test circuits. The project will result in design methodologies that improve the security of computing and communication chips through new on-chip capabilities for the detection of malicious hardware. This first effort to detect adverse circuits with on-chip temperature sensors has the benefit that local power dissipations from numerous locations on the chip can be monitored without requiring a large number of additional pins or exposing the surface of the chip. Hence, the system can become a tool to ensure the integrity of high chip volumes received from "untrusted" manufacturers with simple test setups. Compared to other on-chip power monitoring circuits, the temperature sensors are not electrically connected to the supply voltage path or any internal nodes of the functional circuits. Therefore, the proposed approach will overcome the performance degradation problems associated with monitoring sensitive high-speed digital circuits and high-frequency analog circuits. Furthermore, a methodology to use temperature sensors for on-chip static and dynamic power detection will be advanced, which offers a non-invasive alternative to conventional power detectors in other built-in testing applications.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Oct 15, 2018
- Source ID
- W911NF1710411
Entities
People
- Marvin Onabajo
Organizations
- Army Contracting Command
- Northeastern University
- United States Army