A Productive Open Source Hardware Development Flow
Abstract
This proposal ask for resources to improve the productivity of hardware designers. The resulting infrastructure aims at becoming the core of hardware designers tools by allowing large scale designs, incremental elaboration/synthesis/simulation, leverage multicores, and cloud. We call this project LGraph for the Live Graph that resides at its core. LGraph is designed to become the next LLVM-like infrastructure for hardware design with a focus on fast response time for large designs. Current tools, commercial and academic, do not scale well with large designs. This lack of scalability is shown in compilation, simulation, and verification. As the designs scale in size, the tools get very long compilation times, long synthesis feedback loops, and even slower simulations. While software flows are used to fast incremental flows, hardware designers need to wait hours to get feedback. The goal of this project is that for synthesis and simulation a small code change even for a large project should complete in a few seconds. In addition, other time consuming tasks like formal verification or design frequency improvement should also finish in few seconds. The proposal includes details by providing incremetal elaboration, scalable synthesis, incremental simulation with Hot Reload, scalable simulation. All these changes while providing more correct by construction transformations with elastic pipelines and third party tools. If funded, the team will be directed by PI Renau and co-PI Beamer at UC Santa Cruz.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 04, 2019
- Source ID
- W911NF1910466
Entities
People
- Jose Renau
Organizations
- Army Contracting Command
- National Security Agency
- University of California, Santa Cruz