Layered Approximate Hardware Computing with Meta-Reasoning Capabilities
Abstract
Publicly releasable project abstract Approximate computing is an emerging paradigm that enables trade-off of computational accuracy with computational resources such as runtime, hardware area and power consumption. This paradigm is perfectly suited for application domains that are inherently error tolerant, such as image/video processing, deep neural networks, machine learning, and computer graphics. The goal of this proposal is to create a new class of layered approximate hardware systems that are able to gracefully trade-off accuracy with power consumption. To achieve the proposed goal, the PI proposes a new layered approach to approximate hardware (HW) computing, where each HW layer can be enabled in a cascaded manner to gradually improve accuracy at the expense of additional power consumption. There is a core HW layer that provides a minimum Quality-of-Results (QoR) for the circuit with minimum power consumption. If this minimum QoR is not acceptable then additional HW layers are enabled to boost accuracy at the expense of additional power consumption. To synthesize the HW layers, we propose techniques based on Boolean Matrix Factorization (BMF) that can be applied to any general circuit. We demonstrate strong preliminary results for BMF-based circuit approximations, where one can achieve large dynamic ranges in power consumption (reaching 1-5x) with a small trade-off in accuracy (0-20%). Furthermore, we propose specialized techniques that can exploit the application structure to generate the HW layers. We consider applications in video processing and deep learning. To enable dynamic activation of HW layers during runtime, we propose the design of a meta-reasoner controller that monitors the QoR from the circuit during runtime and enables additional HW layers to boost accuracy when needed, or disables HW layers to reduce the power consumption whenever the QoR is above the acceptable limit. Our proposed layered approach provides a flexible way in HW to trade-off power consumption and QoR. We also explore the synergy between the proposed approximation methods and inexact probabilistic computing methods. In particular, we propose a technology mapping methodology that assigns the constructed approximate HW layers to the available probabilistic technology substrates to minimize the overall probability of error. The proposed project will lead to a software tool that enable designers to automatically synthesize approximate circuits, where QoR and power consumption can be traded gracefully. Furthermore, the project will lead to hardware prototypes as proof-of-concept for the proposed methods. The hardware prototypes will focus on applying the proposed methods to important applications in video processing and deep learning. The tool and prototypes will provide the researchers at DoD ARO with the tools and technology required to realize power-efficient computing circuits using approximate computing techniques.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Sep 04, 2019
- Source ID
- W911NF1910484
Entities
People
- Sherief Reda
Organizations
- Army Contracting Command
- Brown University
- National Security Agency