Energy efficient hardware acceleration of stochastic computing for solving optimization problems and implementing probabilistic neural networks
Abstract
As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence (AI), deep learning (DL), and Big-data, a change in paradigm that can trade precision for energy and resource efficiency without severely compromising on the computation speed is being sought for many applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates. Furthermore, many computationally demanding combinatorial optimization problems such as Travelling Salesman Problem (TSP), Ising spin glass system, etc., can be accelerated using SC. Finally, several brain-inspired and probabilistic machine learning (ML) algorithms and inference approaches can benefit from SC. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, and the von Neumann bottleneck separating memory and logic, make it less attractive. Memristor and spin-based devices offer natural randomness and Òin-memory computeÓ advantages but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here we propose to overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors. We also propose to use the monolithic SC architecture to accelerate stochastic arithmetic for image processing, solve various combinatorial optimization problems such as integer factorization, TSP etc., using metaheuristic algorithms such as Ant Colony Optimization (ACO), and Simulated Annealing (SA), and implement probabilistic learning and inference for neural networks using stochastic neurons and synapses. For all tasks, our objective is to achieve several orders of magnitude reduction in the energy expenditure using smaller hardware footprint and without compromising severely on computational speed and accuracy.
Document Details
- Document Type
- DoD Grant Award
- Publication Date
- Jul 27, 2023
- Source ID
- W911NF2310279
Entities
People
- Saptarshi Das
Organizations
- Army Contracting Command
- National Security Agency
- Pennsylvania State University