Gratings of Regular Arrays and Trim Exposures (GRATE)
Abstract
(U)The Gratings of Regular Arrays and Trim Exposures (GRATE) program will develop revolutionary circuit design methodologies combined with hybrid lithography tools to enable cost-effective low volume nanofabrication for DoD applications. Moore’s law has driven the silicon industry for several decades with the minimum feature size on an integrated circuit (IC) reduced to 45 nm for today’s commercial products. Due to challenging patterning requirements and complex circuit designs, costs of lithography tools and masks have become unaffordable for low-volume manufacture, i.e., military electronics or application specific integrated circuit (ASICs). Similarly, the circuit design, verification, and testing costs have also grown exponentially further preventing military electronics from using advanced silicon technology nodes. Military electronics capabilities are currently limited by the high cost of nanofabrication. To solve this important problem, DARPA has invested in a variety of maskless patterning technologies including parallel e-beam arrays, parallel scanning probe arrays, and an innovative e-beam lithography tool. This program will develop revolutionary circuit design methodologies coupled with innovative hybrid maskless patterning tools to realize cost-effective nanofabrication for low-volume defense or commercial ASICs. Such an approach can also address the nanofabrication requirements of other low-volume DoD technologies such as photonics and micro-electro-mechanical systems. This program will transition via industry.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2011
- Source ID
- a03ed32368b188b665247bec64a665aa