Gratings of Regular Arrays and Trim Exposures (GRATE)
Abstract
The goal of the Gratings of Regular Arrays and Trim Exposures (GRATE) program is to develop revolutionary circuit design methodologies combined with innovative fabrication techniques to enable cost-effective, low-volume fabrication of application specific integrated circuits (ASICs) for DoD applications. The design methodologies will enable a simplified physical layout implementation of circuits by using extremely regular geometries without sacrificing circuit density or performance. These simplified circuit designs will be implemented using high-resolution grating patterns that can be fabricated at high-throughput using either mask-based or maskless lithography. The methodologies developed in this program are expected to reduce significantly the design costs of high-performance DoD ASICs at the advanced complementary metal-oxide semiconductor (CMOS) technology nodes.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2014
- Source ID
- b87c30d886dccc7c118376f08dd8ee8d