Fast and Big Mixed-Signal Designs (FAB)
Abstract
Developing capabilities to intermix and tightly integrate silicon processes which are currently supported at different scaling nodes and by different vendors is critical to increasing the capabilities of high-performance military microelectronics. For example, silicon-germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) processes allow CMOS logic to be integrated with radio frequency (RF) heterojunction bipolar transistors (HBTs), which enables mixed-signal circuits having RF analog capabilities tightly coupled to digital processing. However, the SiGe process flow was developed to integrate to a single CMOS technology node and significant design and engineering effort is required to retarget the flow for a new node. Thus, BiCMOS processes tend to lag behind commercial CMOS by several generations. This program will investigate the potential for a truly process-agnostic integration technology that is inclusive of any current or future circuit fabrication technology such as GaAs, GaN and SiGe with a standardized interconnect topology. Such a technology platform will enable the design of individual circuit IP blocks, such as low-noise amplifiers and analog-to-digital converters, with a goal of re-use of the intellectual property (IP) across applications. Re-use will allow the DoD to amortize the upfront design cost of these blocks over several designs instead of leveling the burden on a single program. Furthermore, the IP can be designed in the fabrication process best suited for the performance goals and evolve more quickly than larger, more expensive single chip systems-on-a-chip. Through standardization of the interface, FAB will enable the DoD to leverage the advancements driven by the global semiconductor market rather than relying on a single on-shore foundry provider or on proprietary circuit designs owned by a handful of traditional prime performers. In the Applied Research part of this program, focus will be placed on the rapid development and insertion of microsystems utilizing SiGe technology with 14nm Si CMOS. The development of a SiGe fabrication process integrated with 14 nanometer Silicon CMOS will be explored. This program has advanced technology development efforts funded in PE 0603739E, Project MT-15.
Document Details
- Document Type
- Accomplishment
- Publication Date
- Oct 01, 2016
- Source ID
- ebc08b39467f9af08b6306e98d12b1fd
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- Root: ELECTRONICS TECHNOLOGY