Digital Signal Processor for a Test-Bed Ocean-Surveillance Radar
Abstract
A digital signal processor for a scaled-down test-bed model of a satellite ocean-surveillance radar system has been developed. This processor employs a digital-feedback integrator technique to achieve improved system signal-to-noise-plus-clutter characteristics required for automatic detection. State-of-the-art integrated circuitry is used, including large-scale-integrated (LSI) high-speed shift registers. The radar video is processed and digitally compared to a threshold level adaptively determined from separately processed average clutter-plus-noise data to determine the occurrence of detections. The processor also includes provision for the recording of radar-video, timing, and antenna-rotation data on magnetic tape during flight testing. These tapes then form a library of radar flight data that are subsequently decoded and processed at the laboratory.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 26, 1971
- Accession Number
- AD0517510
Entities
People
- L. M. Leibowitz
- R. K. Baldauf
Organizations
- United States Naval Research Laboratory