Full Custom Integrated Circuit (IC) Design Flow at U.S. Army Research Laboratory

Abstract

The steps required to set up and run the Cadence Full Custom Integrated Circuit Design Flow are given in detail. Included is a walkthrough showing the design of an inverter, from schematic capture through layout, including design rule check (DRC), layout versus schematic (LVS) and parasitic extraction.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 2011
Accession Number
AD1043295

Entities

People

  • James R. Wilson

Organizations

  • United States Army Research Laboratory

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Buildings And Structures
  • Circuits
  • Directories
  • Electronics Laboratories
  • Errors
  • Extraction
  • Hierarchies
  • Integrated Circuits
  • Inverters
  • Metal Oxide Semiconductors
  • Military Research
  • Operating Systems
  • Procurement
  • Radio Frequency
  • Semiconductors
  • Simulations
  • Simulators

Fields of Study

  • Physics

Readers

  • Computer Vision.
  • Integrated Circuit Design and Technology.