A 56GS/s 8 bit Time Interleaved Analog to Digital Converter

Abstract

This paper presents a 56GS/s 8-bit time-interleaved analog to digital converter (ADC) with an integrated JESD204Binterface implemented in the 28nm RF CMOS node. ADC block architectures, advanced calibration techniques, a top-level layout, a chip carrier, and initial considerations for the test printed circuit board (PCB) are discussed. Based on the simulation results, the ADC core achieves the expected 6-bit value of effective number of bits (ENOB) at 56GS/s at an input frequency of 20GHz while dissipating 420mW. On-chip calibration mechanisms are employed in the ADC to suppress the spurs in the ADC output spectrum caused by the usage of time-interleaving techniques. This feature extends the ADC's application to phased array radars, radio telescopes, and lO0Gb/s fiber optic receivers.

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Document Details

Document Type
Technical Report
Publication Date
Mar 25, 2019
Accession Number
AD1075720

Entities

People

  • Anton Karnitski
  • Chris Gill
  • Dalius Baranauskas
  • Denis Zelenin
  • Gytis Baranauskas

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Calibration
  • Circuit Boards
  • Circuits
  • Communication Systems
  • Connectors
  • Conversion
  • Converters
  • Field Programmable Gate Arrays
  • Frequency
  • High Performance Computing
  • Power Supplies
  • Printed Circuit Boards
  • Printed Circuits
  • Sampling
  • Simulations
  • Test And Evaluation
  • Transmission Lines

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Systems Analysis and Design

Technology Areas

  • Space