DE10 Pins and Connections For Basic MIPS
Abstract
This report describes in detail the pins and connections for the Basic MIPS architecture on a Terrasic DE10-Standard board utilizing an Intel Cyclone V FPGA. Specifically, the detailed connections between one DE10-Standard running Basic MIPS, Temporal Software Redundancy (TSR) MIPS, Triple Modular Redundancy (TMR) MIPS, or Adaptive-Hybrid Redundancy (AHR) MIPS and a second DE10-Standard storing a program in a memory emulator are fully documented.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 12, 2019
- Accession Number
- AD1083728
Entities
People
- Nicolas S. Hamilton
Organizations
- Air Force Institute of Technology