A 112 GS/s Switched-Capacitor DAC in 16 nm FinFET CMOS
Abstract
This paper describes ongoing work toward a FinFET-friendly implementation of high-speed D/A converters for mm-wave arrays. The proposed architecture is based on time interleaved charge redistribution and separates level generation, pulse timing and output power generation. This approach aims to leverage the advantages of 16 nm FinFET technology (transistor speed and density) and simultaneously mitigate its main shortcomings (poor interconnect delay and current handling). Following our proof-of-concept work on 8-bit, 14 GS/s and 28 GS/s prototypes, the current work looks at extending the update rate to112 GS/s using a data and hold interleaving topology. We present preliminary simulation results of the DAC's core circuitry, which exhibits interleaving spurs at -50 dB relative to the signal level.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 29, 2021
- Accession Number
- AD1136317
Entities
People
- Boris Murmann
- Oscar E. Mattia
- P. Caragiulo
Organizations
- Stanford University