DARPA Software Defined Hardware
Abstract
To benchmark the capabilities of novel electronic processing devices being developed by DARPA, six common algorithms, or kernels, were selected to be used for comparison purposes. The kernels include Fast Fourier Transforms, Dense and Sparse Matrix Multiplication, Two Dimensional Convolution, Dijkstra's Algorithm, and the Auction Algorithm. The processing performance of these kernels on new devices, in terms of speed and power requirements, are to be compared against the performance on modern Application Specific Integrated Circuits (ASICs). Since ASICs for these specific kernels are not equally available, Field Programmable Gate Arrays (FPGAs) are used as proxies. For each kernel, an operations per watt value is derived when implemented on FPGAs, from which the metric for ASIC performance is estimated.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 2021
- Accession Number
- AD1145204
Entities
People
- Jonathan P. Skeans
Organizations
- University of Dayton