Thermal-Mechanical Stress Limitations for Through- Wafer Vias and Implications for Wafer-Level Packaging
Abstract
Solid copper through-silicon vias (TSVs) fabricated in silicon (Si)-on-insulator wafers failed during subsequent thermal processing. A study of stress, induced by coefficient of thermal expansion (CTE) mismatch with the surrounding Si, was conducted as a cause of failure mechanisms for the TSVs. Three-dimensional thermal-mechanical models of via structures under the thermal conditions of die-attach (200-300 degrees C) were simulated in ANSYS to gain a better understanding of the thermal stresses seen within the vias and surrounding silicon. Models show that the stress in the copper TSV (>800 MPa) can be well over the yield strength of the material (210 MPa). Further studies were conducted using tungsten (lower CTE, higher yield strength) and hollow-via geometries to find more robust fabrication solutions capable of withstanding higher thermal budgets.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 2021
- Accession Number
- AD1146655
Entities
People
- Henry Gagliardi
- Jeffrey S. Pulskamp
- Robert R. Benoit
- Ryan Knight
Organizations
- Rochester Institute of Technology
- United States Army