Xilinx RF System-on-Chip (RFSoC) 100 Gigabit Ethernet Loop-back Demonstration

Abstract

The ability to move high quantities of instantaneous RF bandwidth data to or from transmitter or receiver processing hardware is paramount to realizing the value of modern RF system-on-chips (RFSoCs), which are staples of many software-defined radio applications. However, practically establishing, initiating, and verifying a working 100 Gigabit Ethernet (100GigE) construction in a high-speed RF construct is not trivial. This report describes practical procedures to implement and observe a 100GigE loop-back demonstration on the Xilinx Generation 1 RFSoC. The authors first discuss the proper initialization of 100GigE hardware and its interconnected RF transmit and receive architecture. Then demonstrated are several working 100GigE loop-back configurations, including single and dual analog-to-Ethernet-to-digital transmissions. Output artifacts are observed on external oscilloscopes, and transmission latency attributed to 100GigE is measured.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2022
Accession Number
AD1156777

Entities

People

  • Edward Viveiros
  • William Diehl

Organizations

  • United States Army Research Laboratory

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Computer Communications
  • Computers
  • Computing System Architectures
  • Connectors
  • Digital Communications
  • Field Programmable Gate Arrays
  • Frequency
  • Frequency Modulation
  • Intellectual Property
  • Modulation
  • Network Protocols
  • Radio Frequency
  • Software Defined Radio
  • Standards
  • Transmitters
  • Waveform Generators
  • Waveforms

Readers

  • Computer Networking
  • Marine Propulsion Engineering and Naval Architecture
  • Parallel and Distributed Computing.