Smash-Software Defined Memory For Optimizing Applications on Advanced Architectures
Abstract
The focus of this work was to develop a Field Programmable Gate Array (FPGA) based memory controller to support shared memory access in a distributed and heterogeneous environment. The FPGA acts as an intermediate buffer between the accelerators and the shared memory. We used the internal memory of the FPGA to buffer data and reduce the memory access latency. We adopted Direct Memory Access (DMA) techniques and caching methods to optimize the memory accesses. This lightweight and reconfigurable memory controller supports a common Flow Control Unit (FLIT) to communicate with different hardware. We investigated different types of FPGAs from various vendors to identify potential candidates. We considered the number of I/O banks, Dynamic Random-Access Memory (DRAM) technologies, support for Universal Serial Bus (USB), average power consumption, and FPGA on-chip memory while selecting the FPGA. We also evaluated various DRAM technologies and DRAMs to identify possible candidates to use as shared memory. In evaluating the DRAMs to choose from, we mainly considered the support for different FPGA technologies, latency, bandwidth, and power consumption. We developed a performance model to verify that our overall system meets the intended performance requirements. Finally, we developed our memory controller using Verilog Hardware Description Language and Xilinx tools. We simulated the design using Xilinxs memory simulation environment to verify its correctness and performance.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 2022
- Accession Number
- AD1162353
Entities
People
- Rajgopal Kannan
- Viktor K. Prasanna
Organizations
- University of Southern California