Rapid Modeling and Analysis Framework for Full-Chip/Package/Board Layout Automation

Abstract

Rapid and accurate layout modeling and analysis at a scale as large as full-chip, complete package and whole board is one of the key enablers to the success of machine generated physical layout in fast CPU run time. Existing layout tools lack such a capability, which has resulted in frequent layout failure and time intensive manual correction of the layout. In this work, PI Jiao has developed algorithms and software for rapid and first-principle-accurate full-chip/package/board layout modeling and analysis, and used such a capability to guide layout synthesis in a fast turnaround time.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2022
Accession Number
AD1183547

Entities

People

  • Dan Jiao

Organizations

  • Purdue University

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Air Force
  • Air Force Facilities
  • Algorithms
  • Central Processing Units
  • Differential Equations
  • Equations
  • Frequency
  • Frequency Domain
  • Governments
  • Integrated Circuits
  • Military Research
  • Paper
  • Partial Differential Equations
  • Simulations
  • Three Dimensional
  • Time Domain
  • Voltage

Fields of Study

  • Engineering

Readers

  • Computational Fluid Dynamics (CFD)
  • Distributed Systems and Data Platform Development
  • Integrated Circuit Design and Technology.