Fabrication Technologies for Superconducting Optoelectronic Neuromorphic Computing
Abstract
In this project, three critical circuit elements (superconducting nanowires, W-center 1.22 um emission centers, and Josephson junctions) for superconducting optoelectronic neuro-morphic computing (SONC) at 300 mm wafer scale using CMOS-fab compatible materials and processes. W-center photoluminescent emission (at a operating temperature of 25 K) of 1.22 micrometers light with less than 3 percent across-wafer non-uniformity was demonstrated. Physical vapor deposited TaN nanowires showed less than 4 percent across-wafer non-uniformity in room temperature resistance, and critical current density of 0.25 MA/sq cm for 20 nm thick nanowires. Cu-encapsulation showed non-hysteretic behavior in the nanowires. Josephson junctions with superconducting -Ta electrodes and ALD TaN as the tunnel barrier showed resistance dependence that scaled precisely as inverse-squared with junction dimension, as expected. Junctions of 2 micrometers showed within wafer non-uniformity of 4 percent, while junctions larger than 500 nm had non-uniformity better than 10 percent. Cryogenic measurements indicated that the tunnel barrier thickness of 9 nm was too thick for determination of Josephson junction critical current, but showed a trace that was otherwise supportive of an SIS junction. Yield of the electrically tested structures exceeded 90 percent. The successful fabrication of these sub-components prepares the ground well for future integration of SONC systems.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 2023
- Accession Number
- AD1194841
Entities
People
- Satyavolu S. Papa Rao
Organizations
- SUNY Polytechnic Institute