Mixed-Mode Circuits For Extreme Speed and Precision

Abstract

The aim of this project, in the phase 2, is to develop a high-frequency phase-locked loop circuit in GF 45nm RFSOI technology with a phase noise specification that is required to be lower than -100 and -120 dBc/Hz at 100 kHz and 1 MHz offset frequencies, respectively. A prototype circuit was designed and fabricated in the target technology, exhibiting -121 and -128 dBc/Hz, respectively, based on lab measurements. Some circuits for characterizing the technology were developed as well.

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Document Details

Document Type
Technical Report
Publication Date
Apr 17, 2024
Accession Number
AD1226266

Entities

People

  • Armin Tajalli

Organizations

  • University of Utah

Tags

Readers

  • Integrated Circuit Design and Technology.