Operation of HTS Digital Circuits at Elevated Temperatures: Beating Thermal Activation
Abstract
Based on the calculations and simulations of digital SFQ and RSQ circuits, which included the kinetic inductance of the circuit, show that a 1-layer technique with HIB-JJs would not work at elevated temperatures. Instead, a 2-layer technique allows to significantly reduce the influence of the kinetic inductance and a 3-layer technique would even allow superconducting wiring with vias. Since the latter is not available, the design proceeded with the 2-layer technique. Combining this 2-layer technique with an additional insulated normal conducting layer (e.g. Au-layer) allows for the design of RQL and SFQ circuits. These circuits have been simulated and will be combine into a test circuit consisting of a dc-to SFQ converter, followed by a JTL, a 2 stage shift register, another JTL and a SFQ-to dc converter.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 17, 2024
- Accession Number
- AD1229721
Entities
People
- Horst Rogalla
Organizations
- Regents of the University of Colorado