Phase I Final Development Report for High-Reliability, Low-Cost Integrated Circuits.
Abstract
The objective of Phase i of this investigation was to develop process feasibility, processing techniques, and automated assembly technology for dual-in-line plastic-packaged integrated circuits. Eight IC's were processed with trimetal interconnections, gold bond bumps and silicon nitride dielectric overcoating. These included three CMOS TTL circuits (5420, 5472, 5470), one Schottky TTL circuit (54S20), three circuits (CD4012B, CD4014A, CD4027A), and one linear circuit (CA741). A universal wafer processing sequence compatible with the requirements of each device type was developed. Electrical parameter specifications were met successfully for each device type. Critical wafer-processing steps have been investigated to determine reproducibility and effects on yield, cost, and reliability. Beam tapes were fabricated from polyimide supported copper and conditions for reproducibly high-strength inner-lead bonds to the device were established. Similarly, outer-lead bonding to plated steel or copper alloy lead frames on high speed automated equipment was facilitated. High-temperature accelerated reliability tests were initiated and problems related to the package materials of construction were analyzed and resolved. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 03, 1977
- Accession Number
- ADA039954