Performance Bounds for Parallel Processors.

Abstract

A general model of computation on a p-parallel processor is proposed, distinguishing clearly between the logical parallelism (p* processes) inherent in a computation, and the physical parallelism (p processor) available in the computer organization. This shows the dependence of performance bounds on both the computation being executed and the computer architecture.

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1976
Accession Number
ADA040873

Entities

People

  • Ruby Bei-loh Lee

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics
  • Weapons Technologies

DTIC Thesaurus Topics

  • Central Processing Units
  • Computations
  • Computer Architecture
  • Computer Programming
  • Computer Science
  • Computers
  • Computing System Architectures
  • Efficiency
  • Electronics
  • Engineering
  • Materials
  • Microarchitecture
  • Military Research
  • New York
  • Parallel Processors
  • Probability
  • United States

Fields of Study

  • Computer science

Readers

  • Distributed Systems and Data Platform Development
  • Theoretical Analysis.

Technology Areas

  • AI & ML