Optimal Layout of CMOS Functional Arrays.

Abstract

Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implemention of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1978
Accession Number
ADA060392

Entities

People

  • T. Uehara
  • W. M. Vancleemput

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics
  • Space
  • Weapons Technologies

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Automation
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Diagrams
  • Electrical Engineering
  • Electronics
  • Electronics Laboratories
  • Integrated Circuits
  • Large Scale Integration
  • Logic
  • Military Research
  • Nand Gates
  • New Jersey
  • New Mexico
  • New York

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Operations Research